An embodiment of the present invention relates to transistors that address drain-induced barrier lowering (DIBL). An embodiment of the present invention relates generally to integrated circuit fabrication. More particularly, an embodiment of the present invention relates to a drain disposed in a substrate.
Advances in semiconductor process technology and digital system architecture have led to integrated circuits having increased operating frequencies. Higher operating frequencies result in undesirable increases in power consumption. Power consumption is a significant problem in integrated circuit design generally, and particularly in large scale, high speed products such as processors and microprocessors.
One way to improve integrated circuit performance, is by reducing the loading capacitance of transistors. Transistor loading capacitance generally has three components, intrinsic gate capacitance, overlap capacitance, and junction capacitance. To reduce junction capacitance, MOSFETs have been constructed on an insulating substrate such as a silicon-on-insulator (SOI) substrate. Typical SOI processes reduce junction capacitance by isolating junctions from the substrate by interposing a thick buried insulator layer. However, short-channel MOSFETs constructed with thick buried insulator layers tend to have poor punch-through characteristics, poor short-channel characteristics and other effects related to the floating body.
FIG. 1 is an elevational cross section of an existing SOI transistor 10. Transistor 10 includes a semiconductive substrate 12, an insulator 14, an isolation structure 16, a semiconductive layer 18 that includes a source/drain region 20, a channel region 22, and a salicided contact landing 24. Transistor 10 also includes a gate electrode 26, a gate dielectric layer 28, and a spacer 30.
A significant issue that arises when dealing with transistors of the present art involves current leakage from the source to the drain. One of the limiting factors in the scaling of transistors to smaller dimensions is the inability of the gate to fully control the channel region 22 below the gate. An electrical field exists between the source or drain 20 and the channel region 22. As the source and drain junctions 32 (the left junction 32 only is indicated with a reference numeral for clarity) approach one another, the lines of force 34 (the electrical field at the right junction 32 only is illustrated for clarity) resulting from the potential that is applied to the drain terminate on the source junction 32, to cause drain-induced barrier lowering (DIBL). DIBL results in a leakage current between the source and drain, and at short enough channel lengths, results in failure of the device.